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rs5c372a/b i 2 c bus serial interface real-time clock ic no.ea-044-160219 1 outline the rs5c372a is a cmos type real-time clock which is connected to the cpu via 2-wires and capable of serial transmission of clock and calendar data to the cpu. the rs5c372a can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems. since an oscillation circuit is driven at a constant voltage, it under goes fluctuations of few voltage and consequently offers low current consumption (typ. 0.5 ? a at 3v). it also provides an oscillator halt sensing function applicable for data validation at power-on and other occa sions and 32-khz clock output for an ex ternal micro computer. (nch. open drain output) the product also incorporates a time tri mming circuit that adjusts the clock with higher precision by adjusting any errors in crystal os cillator frequencies based on signals from the cpu. the crystal oscillator may be selected from 32.768khz or 32.000khz types. integr ated into an ultra compact and ultra thin 8 pin ssop package, the rs5c372a is the optimum choice for equipment requiring small sized and low power consuming products. features ? time keeping voltage: 1.3v to 6.0v ? lowest supply current: 0.5 ? a typ. (0.9 ? a max.) : 3v (25 ? c) (1.0 ? a max.) : 3v ( ? 40 to ? 85 ? c) ? connected to the cpu via only 2 ? wires (i 2 c bus interface, max.400khz, address 7bit) ? a clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, and days of the week) in bcd codes ? interrupt to the cpu (period of one month to one second, interrupt flag, interrupt halt function)( intra , intrb ) ? two systems of alarm functions (days of the week, hours, and minutes) ( intra , intrb ) ? oscillation halt sensing to judge internal data validity ? clock output of 32.768khz (32.000khz) (output controllable via a register) ??? (nch. open drain output) ? second digit adjustment by ? 30 seconds ? automatic leap year recognition up to the year 2099 ? 12-hour or 24-hour time display selectable ? oscillation stabilizing capacity (c g , c d ) incorporated ? high precision time trimming circuit ? oscillator of 32.768kh z or 32.000khz may be used ? cmos logic ? package: 8pin ssop
rs5c372a 2 block diagram comparator_a alarm_a register (week,min,hour) alarm_b register (week,min,hour) comparator_b time counter (sec,min,hour,week,day,month,year) address register address decoder shift register interrupt control 32khz output control divider correc -tion div osc oscin oscout osc detect i/o control v ss scl sd a v dd intra intrb selection guide part number is designated as follows: r s 5c372a - e2 - f ? part number ? ? ? r a 5c372a - bb - c code description a designation of the package. s: ssop8 bb designation of the taping type. only e2 is available. c designation of the lead plating. f: lead free plating fb: sn-bi plating
rs5c372a 3 applications ? communication devices (multi function phone, portable phone, phs or pager) ? oa devices (fax, portable fax) ? computer (desk-top and mobile pc, portable wo rd-processor, pda, electric note or video game) ? av components (portable audio unit, video camera,camera, digital camera or remote controller) ? home appliances (rice cooker, electric oven) ? other(car navigation syst em,multi-function watch) pin configuration ? 8pin ssop intrb 1 scl 2 sda 3 v ss v dd oscin oscout intra 4 8 7 6 5
rs5c372a 4 pin descriptions pin no. symbol name description 2 scl serial clock line this pin is used to input shift clock pulses to synchronize data input/output to and from the sda pin with this clock. up to 6v beyond v dd may be input. 3 sda serial data line this pin inputs and outputs written or read data in synchronization with shift clock pulses from the scl pin. up to 6v beyond v dd may be input. this pin functions as an nch open drain output. 5 intra interrupt output a this pin outputs periodic interrupt pulses and alarm interrupt (alarm_a, alarm_b) to the cpu. this pin is off when power is activated from 0v. this pin functions as an nch open drain output. 1 intrb interrupt output b this pin outputs 32.768khz clock pulses (when 32.768khz crystal is used), periodic interr upt pulses to the cpu or alarm interrupt (alarm_b). it outputs 32.768khz when power source is activated from 0v. this pin functions as an nch open drain output. 7 6 oscin oscout oscillator circuit input/output these pins configure an oscillator circuit by connecting a 32.768khz or 32.000khz crystal oscillator between the oscin-oscout pins. (any other oscillator circuit components are built into the rs5c372a.) 8 4 v dd v ss positive power supply input negative power supply input the v dd pin is connected to the positive power supply and v ss to the ground. absolute maximum ratings (vss ? 0v) symbol item conditions ratinge unit v dd supply voltage ? 0.3 to ? 7.0 v v i input voltag scl, sda ? 0.3 to ? 7.0 v v o1 output voltage 1 sda ? 0.3 to ? 7.0 v v o2 output voltage 2 intra , intrb ? 0.3 to ? 12 p d power dissipation topt ? 25 ? c 300 mw topt operating temperature ? 40 to ? 85 ? c tstg storage temperature ? 55 to ? 125 ? c absolute maximum ratings absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such va lues for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degr adation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits.
rs5c372a 5 recommended operating conditions (vss ? 0v,topt ?? 40 to ? 85 ? c) symbol item conditions min. typ. max. unit v dd supply voltage 1.7 6.0 v v clk timekeeping voltage 1.3 6.0 v f xt oscillation frequency 32.768 or 32.000 khz v pup1 pull-up voltage 1 scl, sda 6.0 v v pup2 pull-up voltage 2 intra , intrb 10.0 v dc characteristics unless otherwise specified: vss ? 0v, v dd ? 3v, topt ?? 40 to ? 85 ? c, oscillation frequency ? 32.768khz, or 32.000khz(r1 ? 30k ? ) symbol item pin name conditions min. typ. max. unit v ih ?h? input voltage scl, sda 0.8v dd 6.0 v v il ?l? input voltage scl, sda ? 0.3 0.2v dd v i ol1 output current intra , intrb v ol1 ? 0.4v 1 ma i ol2 sda v ol2 ? 0.6v 6 ma i ilk input leakage current scl v i ? ? 6v ? 1 1 ? a i oz output off state leakage current sda, intra , intrb v o ? 6v or vss v dd ? 6v ? 1 1 ? a i dd1 standby current v dd v dd ? ? 25 ? c scl, sda ? 3v output ? open ? 1 0.5 0.9 ? a i dd2 v dd v dd ? ?? 40 to ? 85 ? c scl, sda ? 3v output ? open ? 1 1.0 ? a i dd3 v dd v dd ? ? 6v output ? open ? 1 0.8 2.0 ? a c g internal oscillation capacitance 1 oscin 10 pf c d internal oscillation capacitance 2 oscout 10 pf ? 1) the mode outputs no clock pulses w hen output is open (output off state). for consumption current (output: no l oad) when 32khz pulses are output from intrb , see ?usages, 6. typical characteristic measurements?
rs5c372a 6 ac characteristics ? v dd ? 1.7v (supports standard mode i 2 c bus) unless otherwise specified : v ss ? 0v, topt= ? 40 to ? 85, crystal=32.768khz or 32.000khz, input and output conditions:vih=0.8 ? vdd,vil=0.2 ? vdd,vol=0.2 ? vdd,cl=50pf symbol item conditions min. typ. max. unit f scl scl clock frequency 0 100 khz t low scl clock ?l? time 4.7 ? s t high scl clock ?h? time 4.0 ? s t hd ; sta start condition hold time 4.0 ? s t su ; sto stop condition setup time 4.0 ? s t su ; sta start condition setup time 4.7 ? s t su ; dat data setup time 250 ns t hdh ; dat ?h?data hold time 0 ns t hdl ; dat ?l?data hold time v dd ? 2.0v 35 ns t hdl ; dat ?l?data hold time v dd ? 1.7v 150 ns t pl ; dat sda ?l?stable time after falling of scl 2.0 ? s t pz ; dat sda off stable time after falling of scl 2.0 ? s t r rising time of scl and sda (input) 1000 ns t f falling time of scl and sda (input) 300 ns t sp spike width that can be removed with input filter 50 ns ssrp scl sda(in) sda(out) t low t hd;sta t hdh;dat t pz;dat t pl;dat t su;sta t su;sto t high t hd;sta t sp t su;dat sr s start condition stop condition repeated start condition p t hdl;dat ? ) for detailed information refer to ?usages, 1.2 transmission system of i 2 c bus.?
rs5c372a 7 ? v dd ? 2.5v (supports fast mode i 2 c bus) unless otherwise specified : v ss ? 0v, topt= ? 40 to ? 85, crystal=32.768khz or 32.000khz, input and output conditions:vih=0.8 ? vdd,vil=0.2 ? vdd,vol=0.2 ? vdd,cl=50pf symbol item conditions min. typ. max. unit f scl scl clock frequency 0 400 khz t low scl clock ?l? time 1.3 ? s t high scl clock ?h? time 0.6 ? s t hd ; sta start condition hold time 0.6 ? s t su ; sto stop condition setup time 0.6 ? s t su ; sta start condition setup time 0.6 ? s t su ; dat data setup time 100 ns t hdh ; dat ?h?data hold time 0 ns t hdl ; dat ?l?data hold time 35 ns t pl ; dat sda ?l? stable time after falling of scl 0.9 ? s t pz ; dat sda off stable time after falling of scl 0.9 ? s t r rising time of scl and sda (input) 300 ns t f falling time of scl and sda (input) 300 ns t sp spike width that can be removed with input filter 50 ns ssrp scl sda(in) sda(out) t low t hd;sta t hdh;dat t pz;dat t pl;dat t su;sta t su;sto t high t hd;sta t sp t su;dat sr s start condition stop condition repeated start condition p t hdl;dat ? ) for detailed information refer to ?usages, 1.2 transmission system of i 2 c bus.?
rs5c372b i 2 c bus serial interface real-time clock ic 7 outline the rs5c372b is a cmos type real-time clock which is connected to the cpu via 2-wires and capable of serial transmission of clock and calendar data to the cpu. the rs5c372b can generate various periodic interrupt clock pulses lasting for long period (one month), and alarm interrupt can be made by days of the week, hours, and minutes by two incorporated systems. since an oscillation circuit is driven at a constant voltage, it under goes fluctuations of few voltage and consequently offers low current consumption (typ. 0.5 ? a at 3v). it also provides an oscillator halt sensing function applicable for data validation at power-on and other occasions and 32-khz cl ock output for an external micro computer. (cmos output) the product also incorporates a time trimming ci rcuit that adjusts the clock with higher precision by adjusting any errors in crystal oscillator frequencies bas ed on signals from the cpu. the crystal oscillator may be selected from 32.768khz or 32.000khz types. int egrated into an ultra compact and ultra thin 8 pin ssop package, the rs5c372b is t he optimum choice for equipment requiring small sized and low power consuming products. features ? time keeping voltage: 1.45v to 6.0v ? lowest supply current: 0.5 ? a typ. .................. (0.9 ? a max.) : 3v (25 ? c) .......................................................................... (1.0 ? a max.) : 3v ( ? 40 to ? 85 ? c) ? connected to the cpu via only 2-wires (i 2 c bus interface, max.400khz, address 7bit) ? a clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of t he week) in bcd codes ? interrupt to the cpu (period of one month to one second, interrupt flag, interrupt halt function) ( intr ) ? two systems of alarm functions (days of the week, hours, and minutes) ( intr ) ? oscillation halt sensing to judge internal data validity ? clock output of 32.768khz (32.000khz) (output controllable via a register) ??????? (cmos output) ? second digit adjustment by ? 30 seconds ? automatic leap year recognition up to the year 2099 ? 12-hour or 24-hour time display selectable ? oscillation stabilizing capacity (c g , c d ) incorporated ? high precision time trimming circuit ? oscillator of 32.768kh z or 32.000khz may be used ? cmos logic ? package: 8pin ssop
rs5c372b 8 block diagram comparator_a alarm_a register (week,min,hour) alarm_b register (week,min,hour) comparator_b time counter (sec,min,hour,week,day,month,year) address register address decoder shift register interrupt control 32khz output control divider correc -tion div osc oscin oscout 32kout osc detect i/o control v ss scl sd a v dd intr selection guide part number is designated as follows: r s 5c372b - e2 - f ? part number ? ? ? r a 5c372b - bb - c code description a designation of the package. s: ssop8 bb designation of the taping type. only e2 is available. c designation of the lead plating. f: lead free plating fb: sn-bi plating
rs5c372b 9 applications ? communication devices (multi function phone, portable phone, phs or pager) ? oa devices (fax, portable fax) ? computer (desk-top and mobile pc, portable wo rd-processor, pda, electric note or video game) ? av components (portable audio unit, video camera,camera, digital camera or remote controller) ? home appliances (rice cooker, electric oven) ? other(car navigation syst em,multi-function watch) pin configuration ? 8pin ssop 32kout 1 scl 2 sda 3 v ss v dd oscin oscout intr 4 8 7 6 5
rs5c372b 10 pin descriptions pin no. symbol name description 2 scl serial clock line this pin is used to input shift clock pulses to synchronize data input/output to and from the sda pin with this clock. up to 6v beyond v dd may be input. 3 sda serial data line this pin inputs and outputs written or read data in synchronization with shift clock pulses from the scl pin. up to 6v beyond v dd may be input. this pin functions as an nch open drain output. 5 intr interrupt output this pin outputs periodic interrupt pulses and alarm interrupt (alarm_a, alarm_b) to the cpu. this pin is off when power is activated from 0v. this pin functions as an nch open drain output. 1 32kout 32-khz clock output the 32kout pin is used to output 32.768khz clock pulses(when 32.768khz crystal is used).e nabled at power-on from 0volts. cmos output. the rs5c372b can disable 32-khz clock output in response to a command from the host computer. 7 6 oscin oscout oscillator circuit input/output these pins configure an oscilla tor circuit by connecting a 32.768khz or 32.000khz crystal oscillator between the oscin -oscout pins. (any other osc illator circuit components are built into the rs5c372a.) 8 4 v dd v ss positive power supply input negative power supply input the v dd pin is connected to the positive power supply and v ss to the ground. absolute maximum ratings (v ss ? 0v) symbol item conditions ratinge unit v dd supply voltage ? 0.3 to ? 7.0 v v i input voltag scl, sda ? 0.3 to ? 7.0 v v o output voltage 1 sda ? 0.3 to ? 7.0 v output voltage 2 intr ? 0.3 to ? 12 output voltage 3 32kout ? 0.3 to v dd ? 0.3 p d power dissipation topt ? 25 ? c 300 mw topt operating temperature ? 40 to ? 85 ? c tstg storage temperature ? 55 to ? 125 ? c absolute maximum ratings absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such va lues for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degr adation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits.
rs5c372b 11 recommended operating conditions (vss ? 0v,topt ?? 40 to ? 85 ? c) symbol item conditions min. typ. max. unit v dd supply voltage 2.0 6.0 v v clk timekeeping voltage 1.45 6.0 v f xt oscillation frequency 32.768 or 32.000 khz v pup1 pull-up voltage 1 scl, sda 6.0 v v pup2 pull-up voltage 2 intr 10.0 v dc characteristics unless otherwise specified: vss ? 0v, v dd ? 3v, topt ?? 40 to ? 85 ? c, oscillation frequency ? 32.768khz, or 32.000khz(r 1 ? 30k ? ) symbol item pin name conditions min. typ. max. unit v ih ?h? input voltage scl, sda 0.8v dd 6.0 v v il ?l? input voltage scl, sda ? 0.3 0.2v dd v i oh ?h? output current 32kout v oh ? v dd ? 0.5v -0.5 ma i ol1 ?l? output current intr , 32kout v ol1 ? 0.4v 1 ma i ol2 sda v ol2 ? 0.6v 6 ma i ilk input leakage current scl v i ? ? 6v ? 1 1 ? a i oz output off state leakage current sda, intr , 32kout v o ? 6v or vss v dd ? 6v ? 1 1 ? a i dd1 standby current v dd v dd ? ? ? c scl, sda ? 3v output ? open 0.5 0.9 ? a i dd2 v dd v dd ? ?? 40 to ? 85 ? c scl, sda ? 3v output ? open ? 1 1.0 ? a i dd3 v dd v dd ? ? 6v output ? open ? 1 0.8 2.0 ? a c g internal oscillation capacitance 1 oscin 10 pf c d internal oscillation capacitance 2 oscout 10 pf ? 1) the mode outputs no clock pulses w hen output is open (output off state). for consumption current (output: no load) when 32khz pulses are output from 32kout, see ?usages, 6. typical characteristic measurements?
rs5c372b 12 ac characteristics ? v dd ? 2.0v (supports standard mode i 2 c bus) unless otherwise specified : v ss ? 0v, topt ?? 40 to ? 85, crystal ? 32.768khz or 32.000khz, input and output conditions:vih ? 0.8 ? vdd,vil=0.2 ? vdd,vol=0.2 ? vdd,cl=50pf symbol item conditions min. typ. max. unit f scl scl clock frequency 0 100 khz t low scl clock ?l? time 4.7 ? s t high scl clock ?h? time 4.0 ? s t hd ; sta start condition hold time 4.0 ? s t su ; sto stop condition setup time 4.0 ? s t su ; sta start condition setup time 4.7 ? s t su ; dat data setup time 250 ns t hdh ; dat ?h?data hold time 0 ns t hdl ; dat ?l?data hold time 35 ns t hdl ; dat sda ?l?stable time after falling of scl 2.0 ? s t pz ; dat sda off stable time after falling of scl 2.0 ? s t r rising time of scl and sda (input) 1000 ns t f falling time of scl and sda (input) 300 ns t sp spike width that can be removed with input filter 50 ns ssrp scl sda(in) sda(out) t low t hd;sta t hdh;dat t pz;dat t pl;dat t su;sta t su;sto t high t hd;sta t sp t su;dat sr s start condition stop condition repeated start condition p t hdl;dat ? ) for detailed information refer to ?usages, 1.2 transmission system of i 2 c bus.?
rs5c372b 13 ? v dd ? 2.5v (supports fast mode i 2 c bus) unless otherwise specified : v ss ? 0v, topt ?? 40 to ? 85, crystal ? 32.768khz or 32.000khz, input and output conditions:vih ? 0.8 ? vdd,vil=0.2 ? vdd,vol=0.2 ? vdd,cl=50pf symbol item conditions min. typ. max. unit f scl scl clock frequency 0 400 khz t low scl clock ?l? time 1.3 ? s t high scl clock ?h? time 0.6 ? s t hd ; sta start condition hold time 0.6 ? s t su ; sto stop condition setup time 0.6 ? s t su ; sta start condition setup time 0.6 ? s t su ; dat data setup time 100 ns t hdh ; dat ?h?data hold time 0 ns t hdl ; dat ?l?data hold time 35 ns t pl ; dat sda ?l? stable time after falling of scl 0.9 ? s t pz ; dat sda off stable time after falling of scl 0.9 ? s t r rising time of scl and sda (input) 300 ns t f falling time of scl and sda (input) 300 ns t sp spike width that can be removed with input filter 50 ns ssrp scl sda(in) sda(out) t low t hd;sta t hdh;dat t pz;dat t pl;dat t su;sta t su;sto t high t hd;sta t sp t su;dat sr s start condition stop condition repeated start condition p t hdl;dat ? ) for detailed information refer to ?usages, 1.2 transmission system of i 2 c bus.?
rs5c372a/b 14 general description 1. interfacing with the cpu the rs5c372a/b read/write data over i 2 c bus interface via 2-wires: sda (data) and scl (clock). since the output of the i/o pin of sda is open drain, data interfacing with a cpu with different supply voltage is possible by applying pull-up resistor on the circuit board. the maxi mum clock frequency of 400khz of scl enables data transfer in i 2 c bus fast mode. 2. clock function the clock function of the rs5c372a/b allows write/read data from lower two digits of the dominical year to seconds to and from the cpu. when lower two digits of the dominical year are multiples of 4, the year is recognized as a leap year automatically. up to the year 2099 leap years will be automatically recognized. ? ) the year 2000 is a leap year while the year 2100 is not. 3. alarm function ? rs5c372a the rs5c372a has an alarm function t hat outputs an interrupt signal from intra or intrb output pins to the cpu when the day of the week, hour or minute corresponds to the setti ng. these two systems of alarms (alarm_a, alarm_b), each may output interrupt signal se parately at a specified time. the alarm may be selectable between on and off for each day of the week, t hus allowing outputting alarm everyday or on a specific day of the week. the alarm_a is output from the intra pin while the alarm_b is output from either the intra or the intrb pins. polling is possible separately for each alarm function. ? rs5c372b the rs5c372b has an alarm function t hat outputs an interrupt signal from intr output pin to the cpu when the day of the week, hour or minute corresponds to t he setting. these two system s of alarms (alarm_a, alarm_b), each may output interrupt signal separately at a specified time. the alarm may be selectable between on and off for each day of the week, thus allowing outputting alarm everyday or on a specific day of the week. polling is possible separately for each alarm function. 4. high precision time trimming function the rs5c372a/b have an internal os cillation circuit capacitance c g and c d so that an oscillation circuit may be configured simply by externally connecting a crys tal. either 32.768khz or 32.000khz may be selected as a crystal oscillator by setting the inte rnal register appropriately. the rs5c 372a/b incorporate a time trimming circuit that adjusts gain or loss of the clock from the cpu up to approx. ? 189ppm ( ? 194ppm when 32.000khz crystal is used) by approximately 3ppm steps to correct discrepancy in oscillation frequency. (error after correction: ? 1.5ppm: 25 ? c) thus by adjusting frequencies for each system, ? clock display is possible at much higher precision than conventional real-time clock while using a crystal with broader fluctuation in precision. ? even seasonal frequency fluctuation may be corr ected by adjusting seasonal clock error. ? for those systems that have temperat ure detection precision of clock function may be increased by correcting clock error according to temperature fluctuations.
rs5c372a/b 15 5. oscillation halt sensing the oscillation halt sensing function uses a register to store oscillation halt information. this function may be used to determine if the rs5c372a/b supply power has been booted from 0v and if it has been backed up. this function is useful for determining if clock data is valid or invalid. 6. periodic interrupt ? rs5c372a the rs5c372a can output periodic interrupt pulses in addition to alarm function from the intra and intrb pins. this frequency may be selected from 2hz (every 0.5 seco nds), 1hz (every second), 1/60hz (every minute), 1/3600hz (every hour) and monthly (1st of month). output wave form for periodic interrupt may be sele cted from regular pulse waveform (2hz and 1hz) and waveforms (every second, every minute, every hour a nd every month) that are appropriate for cpu level interrupt. outputs may be selected either intra or intrb . the rs5c372a has polling function that monitors pin status in the register. ? rs5c372b the rs5c372b can output periodic interrupt pulses in addition to alarm function from the intr pin. this frequency may be selected from 2hz (every 0.5 seconds) , 1hz (every second), 1/60h z (every minute), 1/3600hz (every hour) and monthly (1st of month). output wave form for periodic interrupt may be sele cted from regular pulse waveform (2hz and 1hz) and waveforms (every second, every minute, every hour a nd every month) that are appropriate for cpu level interrupt. periodic interrupt outputs from intr . the rs5c372b has polling function that monitors pin status in the register. 7. 32-khz clock output ? rs5c372a the rs5c372a may output oscillation frequency from the intrb pin. this clock output is set for output by default, which is set to on or off by setting the register. ? rs5c372b the rs5c372b may output oscillation fr equency from the 32kout pin. this clock output is set for output by default, which is set to on or off by setting the regist er. the 32kout pin is cmos push-pull output terminal. note the year-digit counter of rs5c372a/b counts only lower two digits of a year and no counter is supplied for upper two digits. when you are going to use this prod uct in a system that must cope with ?2000 year problem? which shall be corrected by software.
rs5c372a/b 16 functional descriptions 1. allocation of internal addresses internal address contents data ? 1 a 3 a 2 a 1 a 0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 second counter ? ? 2 s 40 s 20 s 10 s 8 s 4 s 2 s 1 1 0 0 0 1 minute counter ? m 40 m 20 m 10 m 8 m 4 m 2 m 1 2 0 0 1 0 hour counter ? ? h 20 p/ a h 10 h 8 h 4 h 2 h 1 3 0 0 1 1 day of the week counter ? ? ? ? ? w 4 w 2 w 1 4 0 1 0 0 day counter ? ? d 20 d 10 d 8 d 4 d 2 d 1 5 0 1 0 1 month counter ? ? ? mo 10 mo 8 mo 4 mo 2 mo 1 6 0 1 1 0 year counter y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 7 0 1 1 1 time trimming register xsl f 6 f 5 f 4 f 3 f 2 f 1 f 0 8 1 0 0 0 alarm_a (minute register) ? am 40 am 20 am 10 am 8 am 4 am 2 am 1 9 1 0 0 1 alarm_a (hour register) ? ? ah 20 ap/ a ah 10 ah 8 ah 4 ah 2 ah 1 a 1 0 1 0 alarm_a (day of the week register) ? aw 6 aw 5 aw 4 aw 3 aw 2 aw 1 aw 0 b 1 0 1 1 alarm_b (minute register) ? bm 40 bm 20 bm 10 bm 8 bm 4 bm 2 bm 1 c 1 1 0 0 alarm_b (hour register) ? ? bh 20 bp/ a bh 10 bh 8 bh 4 bh 2 bh 1 d 1 1 0 1 alarm_b (day of the week register) ? bw 6 bw 5 bw 4 bw 3 bw 2 bw 1 bw 0 e 1 1 1 0 control register 1 aale bale sl 2 ? 5 sl 1 ? 5 test ct 2 ct 1 ct 0 f 1 1 1 1 control register 2 ? ? 12 /24 adj ? 3 xstp ? 4 clen ctfg aafg bafg ? 1) all the listed data can be read an d written except for adj/xstp. ? 2) the ??? mark indicates data which can be read only and set to ?0? when read. ? 3) the adj/xstp bit of the control register2 is set to adj for write and xstp for read operation. the xstp bit is set to ?0? by writing data into the control register2 for normal oscillation. ? 4) when xstp is set to ?1?, the xsl , f 6 to f 0 , ct 2 to ct 0 , aale, bale, sl 2 , sl 1 , clen and test bits are reset to ?0?. ? 5) sl 1 and sl 2 apply to the rs5c372a. for the rs5c372b, these bits must be filled with ?0?.
rs5c372a/b 17 2. registers 2.1 control register 1 (at internal address eh) d7 d6 d5 d4 d3 d2 d1 d0 aale bale sl 2 ? 2 sl 1 ? 2 test ct 2 ct 1 ct 0 (for write operation) aale bale sl 2 ? 2 sl 1 ? 2 test ct 2 ct 1 ct 0 (for read operation) 0 0 0 0 0 0 0 0 default ? ? 1) the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. ? 2) sl 1 and sl 2 apply to the rs5c372a. for the rs5c372b, these bits must be filled with ?0?. 2.1-1 aale, bale alarm_a, alarm_b enable bits aale, bale description 0 alarm_a (alarm_b) correspondence action invalid (default) 1 alarm_a (alarm_b) correspondence action valid 2.1-2 sl 2 , sl 1 (rs5c372a only) interrupt output select bits sl 2 sl 1 description 0 0 outputs alarm_a, alarm_b, int to the intra . outputs 32k clock pulses to the intrb . (default) 0 1 outputs alarm_a, int to the intra . outputs 32k clock pulses, alarm_b to the intrb . 1 0 outputs alarm_a, alarm_b to the intra . outputs 32k clock pulses, int to the intrb . 1 1 outputs alarm_a to the intra . outputs 32k clock pulses, alarm_b, int to the intrb . by setting sl 1 and sl 2 bits, two alarm pulses (alarm_a and alarm_b), periodic interrupt output (int), 32k clock pulses may be output to the intra or intrb pins selectively. 2.1-3 test test bit test description 0 ordinary operation mode (default) 1 test mode the test bit is used for ic test. set the test bit to 0 in ordinary operation.
rs5c372a/b 18 2.1-4 ct 2 , ct 1 , ct 0 periodic interrupt cycle select bit ct 2 ct 1 ct 0 description wave form mode cycle and falling timing 0 0 0 ? off (?h?) (default) 0 0 1 ? fixed at ?l? 0 1 0 pulse mode 2hz (duty50%) 0 1 1 pulse mode 1hz (duty50%) 1 0 0 level mode every second (synchronized with second count up) 1 0 1 level mode every minute (00 second of every minute) 1 1 0 level mode every hour (00 minute(s) 00 second(s) of every hour) 1 1 1 level mode every month (the 1st day 00 a.m. 00 minut e(s) 00 second(s) of every month) 1) pulse mode : outputs 2hz, 1hz clo ck pulses. for relationships with counting up of seconds see the diagram below. ? ) when 32.000khz crystal is used, in the 2hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternately. duty cycle for 1hz clock pulses becomes 50.4% (?l? duration is 0.496s while ?h? duration is 0.504s). 2) level mode : one second, one minute or one m onth may be selected for an interrupt cycle. counting up of seconds is matched with falling edge of interrupt output. 3) when the time trimming circuit is used, pe riodic interrupt cycle changes every 20 seconds. pulse mode : ?l? duration of output pulses may change in the maximum range of ? 3.784ms ( ? 3.875ms when 32.000khz crystal is used.) for example, duty will be 50 ? 0.3784% (or 50 ? 0.3875% when 32.000khz crystal is used) at 1hz. level mode : frequency in one second may change in the maximum range of ? 3.784ms ( ? 3.875ms when 32.000khz crystal is used.) relation between mode waveforms and ctfg bit ? pulse mode approx. 92 s (32.768khz crystal is used) approx. 94 s (32.000khz crystal is used) ctfg bit (counting up of seconds) intra or intrb pins (intr pin for the rs5c372b) ? ) since counting up of seconds and the falling edge has a time lag of approx. 92 ? s (at 32.768khz) (approx. 94 ? s when 32.000khz crystal is used), time with apparent ly approx. one second of delay from time of the real-time clock may be read when time is read in synchronization with the falling edge of output.
rs5c372a/b 19 ? level mode write 0 to ctfg (second count-up) write 0 to ctfg ctfg bit (second count-up) (second count-up) intra or intrb pins (intr pin for the rs5c372b) 2.2 control register 2 (at internal address fh) d7 d6 d5 d4 d3 d2 d1 d0 ? ? 12 /24 adj clen ctfg aafg bafg (for write operation) 0 0 12 /24 xstp clen ctfg aafg bafg (for read operation) 0 0 undefined 1 0 0 0 0 default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. 2.2-1 12 /24 12 /24-hour time display system selection bit 12 /24 description 0 12-hour time display system (separate for mornings and afternoons) 1 24-hour time display system being set this bit at ?0? indicates 12-hour display system while ?1? indicates 24-hour system. time display digit table 24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11) ? ) either the 12-hour or 24-hour time display sy stem should be selected before writing time data.
rs5c372a/b 20 2.2-2 adj ? 30 second adjust bit adj description 0 ordinary operation 1 second digit adjustment ? the following operations are performed by setting the second adj bit to 1. 1) for second digits ranging from ?00? to ?29? seconds: time counters smaller than seconds are reset and second digits are set to ?00?. 2) for second digits ranging from ?30? to ?59? seconds: time counters smaller than seconds are reset and second digits are set to ?00?. minute digits are incremented by 1. ? second digits are adjusted within 122 ? s (within 125 ? s: when 32.000khz crystal is used) from writing operation to adj. ? the adj bit is for write only and allows no read operation. 2.2-3 xstp oscillator halt sensing bit xstp description 0 ordinary oscillation 1 oscillator halt sensing (default) the xstp bit senses the oscillator halt. ? when oscillation is halted after initial power on from 0v or drop in supply voltage the bit is set to ?1? and which remains to be ?1? after it is restarted. this bit may be used to judge validity of clock and calendar count data after power on or supply voltage drop. ? when this bit is set to ?1?, xsl , f 6 to f 0 , ct 2 , ct 1 , ct 0 , aale, bale, sl 2 , sl 1 , clen and test bits are reset to ?0?. intra ( intr ) ? will stop output and the intrb (32kout) ?? will output 32khz clock pulses. ? the xstp bit is set to ?0? by setting the control register 2 (address fh) during ordinary oscillation. ? ) intra and intrb for the rs5c372a, intr and 32kout for the rs5c372b. 2.2-4 c len 32-khz clock output bit c len description 0 32-khz clock output enabled (default) 1 32-khz clock out put disabled by setting this bit to ?0?, output of clock pulses of the same frequency as the cr ystal oscillator is enabled.
rs5c372a/b 21 2.2-5 ctfg periodic interrupt flag bit ctfg description 0 periodic interrupt output ? off (?h?) (default) 1 periodic interrupt output ? on (?l?) this bit is set to ?1? when periodic interrupt pulses are output ( intra or intrb ? ?l?) ? 1 . the ctfg bit may be set only to ?0? in the interrupt level mode. setting this bit to ?0? sets either the intr a or the intrb to off (?h?) ? 2 . when this bit is set to ?1? nothing happens. ? 1) intr ? ?l? for the rs5c372b. ? 2) intr ? off (?h?) for the rs5c372b. 2.2-6 aafg, bafg alarm_a (alarm_b) flag bit aafg, bafg description 0 unmatched alarm register with clock counter (default) 1 matched alarm register with clock counter ? the alarm interruption is enabled only when the aale, bale bits are set to ?1?. this bit turns to ?1? when matched time is sensed for each alarm. ? the aafg, bafg bit may be set only to ?0?. setting this bit to ?0? sets either the intra or the intrb to the off ?h?. when this bit is set to ?1? nothing happens. ? when the aale, bale bit is set to ?0?, alarm operatio n is disabled and ?0? is read from the aafg, bafg bit. ? ) intr to the off (?h? ) for the rs5c372b. output relationships between the alfg bit and intra or intrb ( intr for the rs5c372b) setting of the aafg (bafg) bit to 0 (matched alarm time) setting of the aafg (bafg) bit to 0 aafg (bafg) bit (matched alarm time) (matched alarm time) intra or intrb pins (intr pin for the rs5c372b)
rs5c372a/b 22 2.3 clock counter (at internal address 0-2h) ? time digit display (in bcd code) second digits : range from 00 to 59 and carried to minute digits when incremented from 59 to 00. minute digits : range from 00 to 59 and carried to hour digits when incremented from 59 to 00. hour digits : see descriptions on the 12 /24 bit (section 2.2-1). carried to day and day-of-the-week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. ? any registered imaginary time should be replaced with co rrect time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. 2.3-1 second digit register (at internal address 0h) d7 d6 d5 d4 d3 d2 d1 d0 ? s 40 s 20 s 10 s 8 s 4 s 2 s 1 (for write operation) 0 s 40 s 20 s 10 s 8 s 4 s 2 s 1 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ? 2.3-2 minute digit register (at internal address 1h) d7 d6 d5 d4 d3 d2 d1 d0 ? m 40 m 20 m 10 m 8 m 4 m 2 m 1 (for write operation) 0 m 40 m 20 m 10 m 8 m 4 m 2 m 1 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ? 2.3-3 hour digit register (at internal address 2h) d7 d6 d5 d4 d3 d2 d1 d0 ? ? p/ a or h 20 h 10 h 8 h 4 h 2 h 1 (for write operation) 0 0 p/ a or h 20 h 10 h 8 h 4 h 2 h 1 (for read operation) 0 0 undefined undefined undefined undefined undefined undefined default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc.
rs5c372a/b 23 2.4 day-of-the-week counter (at internal address 3h) ? day-of-the-week digits are incremented by 1 when carried to 1-day digits. ? day-of-the-week digits display (i ncremented in septimal notation): (w 4 , w 2 , w 1 ) ? (0,0,0) ? (0,0,1) ? ????? ? (1,1,0) ? (0,0,0) ? the relation between days of the week and day-of-the-week digits is user changeable (e.g. sunday ? 0,0,0). ? the (w 4 , w 2 , w 1 ) should not be set to (1, 1, 1). d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? w 4 w 2 w 1 (for write operation) 0 0 0 0 0 w 4 w 2 w 1 (for read operation) 0 0 0 0 0 undefined undefined undefined default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. 2.5 calendar counter (at internal address 4 to 6h) ? the automatic calendar function provides the following calendar digit displays in bcd code. day digits : range from 1 to 31 (for january, ma rch, may, july, august, october, and december). range from 1 to 30 (for april, june, september, and november). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digits when cycled to 1. month digits : range from 1 to 12 and carried to year digits when cycled to 1. year digits : range from 00 to 99 and 00, 04, 08,..., 92, and 96 are counted as leap years. ? any registered imaginary time should be replaced with co rrect time as carrying to such registered imaginary time digits from lower-order ones cause the clock counter malfunction. 2.5-1 day digit register (at internal address 4h) d7 d6 d5 d4 d3 d2 d1 d0 ? ? d 20 d 10 d 8 d 4 d 2 d 1 (for write operation) 0 0 d 20 d 10 d 8 d 4 d 2 d 1 (for read operation) 0 0 undefined undefined undefined undefined undefined undefined default ? 2.5-2 month digit register (at internal address 5h) d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? mo 10 mo 8 mo 4 mo 2 mo 1 (for write operation) 0 0 0 mo 10 mo 8 mo 4 mo 2 mo 1 (for read operation) 0 0 0 undefined undefined undefined undefined undefined default ?
rs5c372a/b 24 2.5-3 year digit register (at internal address 6h) d7 d6 d5 d4 d3 d2 d1 d0 y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 (for write operation) y 80 y 40 y 20 y 10 y 8 y 4 y 2 y 1 (for read operation) undefined undefined undefined undefined undefined undefined undefined undefined default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. 2.6 time trimming register (at internal address 7h) d7 d6 d5 d4 d3 d2 d1 d0 xsl f 6 f 5 f 4 f 3 f 2 f 1 f 0 (for write operation) xsl f 6 f 5 f 4 f 3 f 2 f 1 f 0 (for read operation) 0 0 0 0 0 0 0 0 default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. 2.6-1 xsl bit the xsl bit is used to select a crystal oscillator. set the xsl to ?0? (default) to use 32.768khz. set the xsl to ?1? to use 32.000khz. 2.6-2 f 6 to f 0 the time trimming circuit adjust one second count based on this register readings when second digit is 00, 20, or 40 seconds. normally, counting up to seconds is made once per 32,768 of clock pulse (or 32,000 when 32.000khz crystal is used) generated by the oscillator. setti ng data to this register activates the time trimming circuit. register counts will be incremented as ((f 5 , f 4 , f 3 , f 2 , f 1 , f 0 )?1) ? 2 when f6 is set to ?0?. register counts will be decremented as (( f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) ? 1) ? 2 when f6 is set to ?1?. counts will not change when (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) are set to ( ? , 0, 0, 0, 0, 0, ? ). for example, when 32.768khz crystal is used. when (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) are set to (0, 0, 0, 0, 1, 1, 1), counts will change as: 32,768 ? (7?1) ? 2 ? 32,780 (clock will be delayed) when second digit is 00, 20, or 40. when (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) are set to (0, 0, 0, 0, 0, 0, 1), counts will remain 32,768 without changing when second digit is 00, 20, or 40. when (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) are set to (1, 1, 1, 1, 1, 1, 0), counts will change as: 32,768 ? (?2) ? 2 ? 32,764 (clock will be advanced) when second digit is 00, 20, or 40. adding 2 clock pulses ever y 20 seconds: 2/(32,768 ? 20) ? 3.051ppm (or 3.125ppm when 32.000khz crystal is used), delays the clock by approx. 3ppm. likewise, decrementing 2 cloc k pulses advances the clock by 3ppm. thus the clock may be adjusted to the precision of ? 1.5ppm. note that the time trimming function only adjust clock timing and oscillation frequency and 32-khz clock output is not adjusted.
rs5c372a/b 25 2.7 alarm_a, alarm_b register (alarm_a: internal address 8 to ah; alarm_b: internal address b to dh) 2.7-1 alarm_a minute register (internal address 8h) d7 d6 d5 d4 d3 d2 d1 d0 ? am 40 am 20 am 10 am 8 am 4 am 2 am 1 (for write operation) 0 am 40 am 20 am 10 am 8 am 4 am 2 am 1 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ? 2.7-2 alarm_b minute register (internal address bh) d7 d6 d5 d4 d3 d2 d1 d0 ? bm 40 bm 20 bm 10 bm 8 bm 4 bm 2 bm 1 (for write operation) 0 bm 40 bm 20 bm 10 bm 8 bm 4 bm 2 bm 1 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ? 2.7-3 alarm_a hour register (internal address 9h) d7 d6 d5 d4 d3 d2 d1 d0 ? ? ah 20 , ap/ a ah 10 ah 8 ah 4 ah 2 ah 1 (for write operation) 0 0 ah 20 , ap/ a ah 10 ah 8 ah 4 ah 2 ah 1 (for read operation) 0 0 undefined undefined undefined undefined undefined undefined default ? 2.7-4 alarm_b hour register (internal address ch) d7 d6 d5 d4 d3 d2 d1 d0 ? ? bh 20 , ap/ a bh 10 bh 8 bh 4 bh 2 bh 1 (for write operation) 0 0 bh 20 , ap/ a bh 10 bh 8 bh 4 bh 2 bh 1 (for read operation) 0 0 undefined undefined undefined undefined undefined undefined default ? 2.7-5 alarm_a day-of-the-week register (internal address ah) d7 d6 d5 d4 d3 d2 d1 d0 ? aw 6 aw 5 aw 4 aw 3 aw 2 aw 1 aw 0 (for write operation) 0 aw 6 aw 5 aw 4 aw 3 aw 2 aw 1 aw 0 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ?
rs5c372a/b 26 2.7-6 alarm_b day-of-the-week register (internal address dh) d7 d6 d5 d4 d3 d2 d1 d0 ? bw 6 bw 5 bw 4 bw 3 bw 2 bw 1 bw 0 (for write operation) 0 bw 6 bw 5 bw 4 bw 3 bw 2 bw 1 bw 0 (for read operation) 0 undefined undefined undefined undefined undefined undefined undefined default ? ? )the default means read value when xstp bit is set to ?1 ? by starting up from 0v, or supply voltage drop, etc. ? alarm_a, alarm_b hour register d5 is set to 0 for am and 1 for pm in the 12-hour display system at ap/ a . the register d5 indicates 10 digit of hour digit in 24-hour display system at ah 20 . ? to activate alarm operation, any imaginary alarm time setting should not be left to avoid unmatching. ? in hour digit display midnight is set to 12, noon is set to 32 in 12-hour display system. (see section 2.2-1) ? aw 0 to aw 6 correspond to the day-of-the-week counter (w 4 , w 2 , w 1 ) being set at (0, 0, 0) to (1, 1, 0). ? no alarm pulses are output when all of aw 0 to aw 6 are set to ?0?. example of alarm time settings alarm time settings day-of-the-week 12-hour system 24-hour system sun. aw 0 mon. aw 1 tue. aw 2 wed. aw 3 thu. aw 4 fri. aw 5 sat. aw 6 10-hour 1-hour 10-min 1-min 10-hour 1-hour 10-min 1-min 00:00 am every day 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 01:30 am every day 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 11:59 am every day 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 00:00 pm on monday through friday 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 01:30 pm on sunday 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 11:59 pm on monday, wednesday, and friday 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 designation of days of the week and aw 0 to aw 6 in the above table is an example.
rs5c372a/b 27 usages 1. interfacing with the cpu the rs5c372a/b employ the i 2 c bus system to be connected to the cpu via 2-wires. connection and transfer system of i 2 c bus are described in the following sections. 1.1 connection of i 2 c bus 2-wires, scl and sda which are connected to i 2 c bus are used for transmit clock pulses and data respectively. all ics that are connected to these lines are desi gned that will be not be clamped when a voltage beyond supply voltage is applied to input or output pins. open drain pins are used for output. this construction allows communication of signals between ics with different supp ly voltages by adding a pull-up resistor to each signal line as shown in the figure below. each ic is designed not to affect scl and sda signal lines when power to each of these is turned off separately. v dd 1 v dd 2 v dd 3 v dd 4 scl r p r p sda microcontroller rs5c372a/b other peripheral device ? 1) for data interface, the following conditions must be met: v dd 4 ? v dd 1 v dd 4 ? v dd 2 v dd 4 ? v dd 3 ? 2) when the master is one, the microcontroller is ready for driving scl to ?h? and rp of scl may not be required.
rs5c372a/b 28 cautions on determining rp resistance (1) voltage drop at rp due to sum of input current or output current at off conditions on each ic pin connected to the i 2 c bus shall be adequately small. (2) rising time of each signal shall be kept s hort even when all capacity of the bus is driven. (3) current consumed in i 2 c bus is small compared to the consum ption current permitted for the entire system. when all ics connected to i 2 c bus are cmos type, condition (1) may usually be ignored since input current and off state output current is extremel y small for the many cmos type ics. thus the maximum resistance of rp may be determi ned based on (2) while the minimum on (3) in most cases. in actual cases a resistor may be place between the bus and input/output pins of each ic to improve noise margins in which case the rp minimum value may be determined by the resistance. consumption current in the bus to review (3 ) above may be expressed by the formula below: bus consumption current (sum of input current and off state output current of all devices in stand ? by mode) ? bus stand ? by duration bus stand ? by duration ? bus operation duration ? supply voltage ? ? ? ? ? ? ? supply voltage ? ? ? 2? h in the second member denominator in the above formula is derived from assumption that ?l? duration of sda and scl pins ar e the half of bus operation duration. ? ? 2? in the numerator of the same member is because there are two pins of sd a and scl. the third member, (charging/discharging times per unit time) means number of transition from ?h? to ?l? of the signal line. calculation example is shown below: pull-up resistor (r p ) ? 10k ? , bus capacity ? 50pf (both for scl and sda), v dd ? 3v in as system with sum of input curren t and off state output current of each pin ? 0.1 ? a, i 2 c bus is used for 10ms every second while the rest of 990ms is in the st and-by mode. in this mode number of transitions of the scl pin from ?h? to ?l? state is 100 while sda 50, every second. bus consumption current 0.1 ? ? 990ms 990ms ? 10ms ? 3v ? 10ms ? ?? 2 ? (990ms ? ? 3v ? 50pf ? (100 ? ? 0.099 ? ? 3.0 ? ? ? ? ?
rs5c372a/b 29 1.2 transmission system of i 2 c bus 1.2-1 start and stop conditions in i 2 c bus, sda must be kept at a certain state while sc l is at the ?h? state as shown below during data transmission. t hdl ; dat or t hdh ; dat t su ; dat sda scl the scl and sda pins are at the ?h? level when no data transmission is made. changing the sda from ?h? to ?l? when the scl and the sda are ?h? activates the st art condition and access is started. changing the sda from ?l? to ?h? when the scl is ?h? activates stop co ndition and accessing stopped. generation of start and stop conditions are always made by the master (see the figure below). stop condition t su ; sto t hd ; sta start condition sda scl 1.2-2 data transmission and its acknowledge after start condition is entered, data is transmitted by 1byte (8bits). any bytes of data may be serially transmitted. the receiving side will send an acknowledge signal to t he transmission side each time 8bit data is transmitted. the acknowledge signal is sent immediately after falling to ?l? of scl8bit clock pulses of data transmission, by releasing the sda by the transmission side that has assert ed the bus at that time and by turning the sda to ?l? by the receiving side. when transmission of 1byte data nex t to preceding 1byte of data is received, the receiving side releases the sda pin at falling edge of the scl9bit of clock pulses or when the receiving side switches to the transmission side it starts data transmission. wh en the master is the receiving side, it generates no acknowledge signal after the last 1byte of data from t he slave to tell the transmitter that data transmission has completed when the slave side (transmissi on side) continues to release the sda pin so that the master will be able to generate stop condition. 12 89 acknowledge signal start condition scl from the master sda from the transmission side sda from the receiving side
rs5c372a/b 30 1.2-3 data transmission format in i 2 c bus i 2 c bus generates no ce signals. in place of it each device has a 7bit slave address allocated. the first 1byte is allocated to this 7bit of slave address and to the command (r/ w ) for which data transmission direction is designated by the data transmission thereafter. 7bit address is sequentially transmitted from the msb and 2 and after bytes are read, when 8bit is ?h? and write when ?l?. the slave address of the rs5c372 a/b are specified at (0110010). at the end of data transmission/receiving stop condition is generated to complete transmission. however, if start condition is generated without generating stop condition, repeated start condition is met and transmission/receiving data may be continued by setting the slave address again. use this procedures when the transmission direction needs to be changed during one transmission. s master to slave start condition p slave to master stop condition sr repeated start condition aa acknowledge signal a s0a a ap r/w=0 (write) (0110010) data is written into the slave from the master when data is read from the slave immediately after 7bit addressing from the master when the transmission direction is to be changed during transmission. s1a a p r/w=1 (read) (0110010) s 0 a a sr 1 r/w=0 (write) (0110010) r/w=1 (read) (0110010) aa p inform read has been completed by not generating an acknowledge signal, to the slave side. inform read has been completed by not generating an acknowledge signal, to the slave side. a a slave address slave address slave address slave address data data data data data data data
rs5c372a/b 31 1.2-4 data transmission write format in the rs5c372a/b although the i 2 c bus standard defines a transmission format for the slave address allocated for each ic, transmission method of address information in ic is not defined. the rs5c372a/b transmit data the internal address pointer (4bit) and the transmission format register (4bit) at the 1byte next to one which transmitted a slave address and a write command. for write operation only one transmission fo rmat is available and (0000) is set to the transmission format register. the 3byte transm its data to the address specified by the internal address pointer written to the 2byte. internal address pointer se ttings are automatically incremented for 4byte and after. note that when the internal address pointer is fh , it will change to 0h on transmitting the next byte. example of data writing (when writing to internal address eh to fh) s 0 110 0 0 1 0 1 110 00 0 0 aaa p a r/w=0 (write) transmission of slave address (0110010) setting of eh to the internal address pointer setting of 0h to the trans- mission format register writing of data to the internal address eh. writing of data to the internal address fh. data data s aa master to slave start condition acknowledge signal a p slave to master stop condition
rs5c372a/b 32 1.2-5 data transmission read format of the rs5c372a/b the rs5c372a/b allow the following three readout methods of data from an internal register. 1) the first method to reading data from the internal re gister is to specify an internal address by setting the internal address pointer and the transmission format register described 1.2-4, generate the repeated start condition (see section 1.2-3) to change the data trans mission direction to perform reading. the internal address pointer is set to fh when the stop condition is met. therefore, this method of reading allows no insertion of the stop condition before the repeated start condition. set 0h to the transmission format register. example 1 of data read (when data is read from 2h to 4h) s 0 110 0 0 1 0 0 010 00 0 0 a aaap a1 0 sr 0 010 a 1 1 r/w=0 (write) transmission of slave address (0110010) transmission of slave address (0110010) setting of 2h to the internal address pointer setting of 0h to the trans- mission format register reading of data from the internal address 2h. reading of data from the internal address 3h. reading of data from the internal address 4h. data data data repeated start condition r/w=1 (read) ssr aa master to slave slave to master start condition acknowledge signal repeated start condition p stop condition a
rs5c372a/b 33 2) the second method to reading data from the internal regi ster is to start reading immediately after writing to the internal address pointer and the transmission format register. although this method is not based on the i 2 c bus standard in a strict sense it still effective to shorten read time to ease load to the master. set 4h to the transmission format register when this method is used. example 2 of data read (when data is read from internal addresses eh to 1h). s 0 110 0 0 1 0 1 110 00 1 0 a a sp aa aap aa r/w=0 (write) transmission of slave address (0110010) setting of eh to the internal address pointer setting of 4h to the trans- mission format register reading of data from the internal address fh. master to slave slave to master start condition acknowledge signal stop condition reading of data from the internal address 0h. reading of data from the internal address 1h. reading of data from the internal address eh a data data data data
rs5c372a/b 34 3) the third method to reading data from the internal regi ster is to start reading immediately after writing to the slave address and the r/ w bit. since the internal address pointer is set to fh by default as described in 1), this method is only effective when reading is started from the internal address fh. example 3 of data read (when data is read from internal addresses fh to 3h). s 0 110 1 0 1 0a a sp aa aap aa r/w=1 (read) transmission of slave address (0110010) reading of data from the internal address fh. reading of data from the internal address 1h. master to slave slave to master start condition acknowledge signal stop condition reading of data from the internal address 2h. reading of data from the internal address 3h. reading of data from the internal address 0h. a data data data data data
rs5c372a/b 35 1.2-6 data transmission under special condition the rs5c372a/b hold the clock tentativ ely for duration from start condition to stop condition to avoid invalid read or write clock on carrying clock. when clock is carried during this period, which will be adjusted within approx. 61 ? s from stop condition. to prevent invalid read or write clock shall be made during one transmission operation (from start condition to stop condition). when 0.5 to 1.0 second elapses after start condition any access to the rs5c372a/b are automatically released to release tentative hold of the clock, set fh to the address pointer, and access from the cpu is forced to be te rminated (the same action as made stop condition is received: automatic resume function from the i 2 c bus interface). therefore, one access must be completed within 0.5 seconds. the automatic resume function pr events delay in clock even if the scl is stopped from sudden failure of the system during clock read operation. also a second start condition after the first condit ion and before the stop condition is regarded as the ?repeated start condition.? therefore, when 0.5 to 1.0 seconds passed after t he first start condition, access to the rs5c372a/b are automatically released. if access is tried after automatic resume function is activated, no acknowledge signal will be output for writing while ffh will be output for reading. access to the real-time clock 1) no stop condition shall be generated until cl ock read/write is started and completed. 2) one cycle read/write operation shall be completed within 0.5 seconds. 3) do not make start condition within 62 ? s from stop condition. when clock is carried during the access, which will be adjusted within approx.61 ? s from stop condition. the user shall always be able to access the real-time clock as long as these three conditions are met. bad example of reading from seconds to hours (invalid read) (start condition) ? (read of seconds) ? (read of minutes) ? (stop condition) ? (start condition) ? (read of hour) ? (stop condition) assuming read was started at 05:59:59 p.m. and whil e reading seconds and minutes the time advanced to 06:00:00 p.m. at this time second digit is hold so the read as 05:59:59. t hen the rs5c372a/b confirm (stop condition) and carry second digit being hold and the time changes to 06:00:00 p.m. then, when the hour digit is read, it changes to 6. the wrong results of 06:59:59 will be read.
rs5c372a/b 36 2. configuration of oscillating circuit and time trimming 2.1 configuration of oscillating circuit 8 7 6 rs5c372a/b r f r d c d c g oscin oscout 32khz v dd v dd a typical external device: x'tal: 32.768khz or 32.000khz (r 1 ? 30k ? typ.) (c l ? 6pf to 8pf) typical values of internal devices: r f 15m ? (typ.) r d 60k ? (typ.) c g , c d 10pf (typ.) the oscillation circuit is driven at a constant voltage of about 1.2v relative to the vss level. consequently, it generates a wave form having a peak-to-p eak amplitude of about 1.2v on the positive side of the vss level. considerations on crystal oscillator basic characteristics of a crystal oscillator includes r 1 (equivalent series resistanc e: ease of oscillation) and c l (load capacitance: rank of center frequency). r 1 ? typ. of 30k ? , c l ? 6 to 8pf is recommended for the rs5c372a/b. confirm recommended values to the m anufacturer of the crystal oscillator used. considerations in mounting compon ents surrounding oscillating circuit 1) mount the crystal oscillators in t he closest possible position to the ic. 2) avoid laying any signal or power li ne close to the oscillation circuit (particularly in the area marked with ? ? a ? ? in the above figure). 3) apply the highest possible insulation resistance between the oscin or oscout pin and the pcb. 4) avoid using any long parallel line to wire the oscin and oscout pin. 5) take extreme care not to cause condensation, whic h leads to various problems such as oscillation halt. other relevant considerations 1) when applying an external input of clock pulse s (32.768khz or 32.000khz) to the oscin pin: dc coupling : prohibited due to mismatching of input levels. ac coupling : permissible except that unpredictabl e results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) avoid using the oscillator output of the rs5c372a/b (from the oscout pin) to drive any other ic for the purpose of ensuring stable oscillation.
rs5c372a/b 37 2.2 measurement of oscillation frequency frequency counter rs5c372a/b 32.768khz or 32.000khz oscin oscout v dd v ss intrb (32kout) * 4 * 4 * 3 *1) clock pulse of 32.768khz or 32.000khz is output from the intrb output pin on powering on (xstp is set to 1). *2) use a frequency counter having at least 6 digits (7digits or more recommended). *3) pull-up the intrb output pin to v dd for the rs5c372a. *4) intrb applies to the rs5c372a, and 32kout applies to the rs5c372b. the rs5c372b does not need pull-up resistor. 2.3 oscillation frequency adjustment adjustment amount of oscillation frequency may diff er dependent on how the rs5c372a/b is used or how much clock error is permissible in the sy stem it is installed. use the flow chart shown below find an optimal oscillation frequency adjustment method. start 32khz clock used? no no no yes yes yes yes no 32khz clock output is used, but clock frequency precision is not considered for clock precision errors derived by adding deflection in crystal oscillator* 1 + deflection in ic* 2 is permissible* 3 . for clock precision errors derived by adding deflection in crystal oscillator* 1 + deflection in ic* 2 is permissible* 3 . (a) course (b) course (c) course (d) course *1) in general crystal oscillators are cla ssified by their central frequency of c l (load capacitance) and available further grouped in several ranks as ? 10, ? 20 and ? 50ppm of fluctuations in precision. *2) fluctuations in frequency due to the ic used is generally from ? 5 to ? 10ppm at a room temperature. *3) clock precision here is at a room temperature and is subjected to change due to temperature characteristics of the crystal itself.
rs5c372a/b 38 (a) course adjustment of clock is not m ade for ic (no adjustment) and any c l value may be used for the crystal oscillator. precision fluctuations of a crystal os cillator may be selected as long as cloc k precision allows. obtain the central frequency as described in section 2.2 using several crysta l oscillator and ics, determine an adjustment value as described in ?2.4 time trimming circuit? which shall be set to the rs5c372a/b. (b) course to keep clock precision within the range of (fluctuation in crys-tal oscillator ? fluctuation in ic), clock shall be adjustment is required for each ic. on adjusting procedures see ?2.4 time trimming circuit.? available selection range for the frequency precision fluctuations and c l (load capacitance) for a crystal oscillator may be widened by adjusting clock frequency. obtain the central frequency as described in section 2.2 using the crystal oscillator and ic to be used, determine if an adjustment is possib le or not using the clock adjustment circuit, perform adjustment for each ic using the clock adjustment circuit. up to ? 1.5ppm may be adjusted at a room temperature. (c) course in (c) and (d) courses, adjustment of 32-khz clock output frequency as well as clock is necessary. frequency adjustment for the crystal oscillator is made by adjusting both of c g and c d connected to the both ends of the oscillator. since the rs5c 372a/b incorporate the c g and c d , oscillating frequency is required using c l of the crystal oscillator as the reference. generally, relation between c l and c g or c d is as follows: c l ? c g ?? c d ? c s c s : board floating capacitance c g ? c d although a crystal oscillator having c l value of around 6 to 8pf is recommended for the rs5c372a/b, measure oscillation frequency as described in section 2. 2 and if frequency is high (clock gains) switch to a crystal oscillator with smaller c l while if frequency is small (clock loses) switch to an oscillator with larger c l . using these procedures select a crystal oscillator with optimal c l and set unadjusted value to the clock adjustment circuit. (see section 2.4, ?time trimming circuit?.) we recommend to consult the crystal manufacturer on compatibility of c l values. high oscillation frequency (clock gains) may be adjusted by externally adding c gout as shown below. 8 7 6 rs5c372a/b r f r d c d c g oscin oscout 32khz c gout v dd v dd * 1 ? 1) c gout shall be from 0 to 15pf. (d) course select a crystal oscillator as in the (c) course, then adju st clock error for each ic as in (b) course. for clock adjusting procedures, see ?2.4 time trimming circuit.?
rs5c372a/b 39 2.4 time trimming circuit using the time trimming circuit gain or lose of cloc k may be adjusted with high precision by changing clock pulses for one second every 20 seconds. when adjustment with this circuit is not necessary, set (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) to ( ? , 0, 0, 0, 0, 0, ? ) to disable adjustment. ( ? mark indicates 0 or 1.) adjustment amount may be calculated using the following formula. 2.4-1 when oscillation frequency ? 1 >target frequency ? 2 (clock gains) adjustment amount ? 3 ? (oscillation frequency ? ? ? ? ? 6 (oscillation frequency ? ? ? ? ? ? ? 1) oscillation frequency : cl ock frequency output from the intrb (32kout for the rs5c372b) pin as in ?2.2 oscillation frequency measur ement? at a room temperature. ? 2) target frequency : a frequency to be adjusted to. since temperature characteristics of a 32.768khz crystal oscillator are such that it will generally generates the highest frequency at a r oom temperature, we recommend to set the target frequency to approx. 32768.00hz to 32768.10hz ( ? 3.05ppm to 32768hz). we also recommend setting of approx. 32000.00hz to 32000.10hz (3.125ppm to 32000hz) also for the 32.000khz crystal. note that this value may differ based on the environment or place where the device will be used. ? 3) adjustment amount : a value to be set finally to f6 to f0 bits. this value is expressed in 7bit binary digits with sign bit (two's compliment). 2.4-2 when oscillation frequency ? target frequency (no clock gain or loss) set the adjustment value to 0 or ? 1, or ? 64 or ? 63 to disable adjustment. 2.4-3 when oscillation frequency rs5c372a/b 40 example of calculations (1) when oscillation frequency ? 32768.85khz ; target frequency ? 32768.05khz adjustment value ? (32768.85-32768.05 ? 0.1) / (32768.85 ? 3.051 ? 10 ? 6 ) (32768.85 ? 32768.05) ? 10 ? 1 ? 9.001 ? 9 set (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) to (0, 0, 0, 1, 0, 0, 1). as this example shows, adjustments to be used wh en the clock gains shall be distance from 01h. (2) when actual oscillation frequency ? 32763.95khz ; target frequency ? 32768.05khz adjustment value ?? (32763.95-32768.05) / (32763.95 ? 3.051 ? 10 ? 6 ) (32763.95-32768.05) ? 10 ?? 41.015 ? 41 to express ? 41 in 7bit binary digits with sign bit (two's compliment), subtract 41(29h) from 128(80h) in the above case, 80h-29h ? 57h. thus, set (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) to (1, 0, 1, 0, 1, 1, 1). as this example shows, adjustments to be used when the clock loses shall be distance from 80h. after adjustment, adjustment error agains t the target frequency will be approx. ? 1.5ppm at a room temperature. notes 1) clock frequency output from the intrb (32kout for the rs5c372b) pin will not change after adjustment by the clock adjustment circuit. 2) adjustable range: the range of adjustment values fo r a case oscillation frequency is higher than target frequency (clock gains) is (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) ? (0, 0, 0, 0, 0, 1, 0) to (0, 1, 1, 1, 1, 1, 1) and actual adjustable amount shall be ? 3.05ppm to ? 189.2ppm ( ? 3.125ppm to ? 193.7ppm for 32.000khz crystal), thus clock error may be adjusted until clock gain reaches ? 189.2ppm ( ? 193.7ppm for 32.000khz crystal). on the other hand, the range of adjustmen t values for a case when oscillation frequency is lower than target frequency (clock loses) is (f 6 , f 5 , f 4 , f 3 , f 2 , f 1 , f 0 ) ? (1, 1, 1, 1, 1, 1, 1) to (1, 0, 0, 0, 0, 1, 0) and actual adjustable amount shall be ? 3.05ppm to ? 189.2ppm ( ? 3.125ppm to ? 193.8ppm for 32.000khz crystal), thus clock error may be adjsted until clock loss reaches ? 189.2ppm ( ? 193.8ppm for 32.000khz crystal). 3) if following 3 conditions are completed, actual cl ock adjustment value could be different from target adjustment value that set by time trimming function. 1. using time trimming function 2. access to rs5c372a/b at random, or synchron ized with external clock that has no relation to rs5c372a/b, or synchronized with periodic interrupt in pulse mode. 3. access to rs5c372a/b more than 2 times per each second on average. for more details, please contact to ricoh.
rs5c372a/b 41 3. oscillator halt sensing oscillation halt can be sensed through monitoring the xstp bit with preceding setting of the xstp bit to 0 by writing data to the control register 2. upon oscillator halt sensing, the xstp bit is switched from 0 to 1. this function can be applied to judge clock data validity. when the xstp bit is 1, xsl , f 6 to f 0 , ct 2 , ct 1 , ct 0 , aale, bale, sl 2 , sl 1 , clen and test bits are reset to 0. ? 1) the xstp bit is set to 1 upon power-on from 0v. note that any instantaneous power disconnection may cause operation failure. ? 2) once oscillation halt has been sensed, the xstp bit is held at 1 even if oscillation is restarted. considerations in use of xstp bit ensure error-free oscillation halt sens ing by preventing t he following events: 1) instantaneous disconnection of v dd 2) condensation on the crystal oscillator 3) generation of noise on the pcb in the crystal oscillator 4) application of voltage exceeding prescribed maxi mum ratings to the individual pins of the ic. in particular, note that the xstp bit may fail to be set to 0 in the presence of any applied supply voltage as illustrated below in such events as backup battery installati on. further, give spec ial considerations to prevent excessive chattering in the oscillation halt sensing circuit. v dd 4. intra output and intrb output pins (rs5c372a), intr output pin (rs5c372b) 4.1 intra output and intrb output pins (rs5c372a) the following three output wave forms can be output from the intra or the intrb pin. 1) alarm interrupt when a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar counter (suchas day-of-the-week, hour or minute) interrupt to the cpu are requested with the output pin being on (?l?). alarm interrupt consists of alarm_a and alarm_b, both have equivalent functions. 2) periodic interrupt outputs an output wave form selected by setting the per iodic interrupt frequency select bit. wave forms include pulse mode and level mode. 3) 32-khz clock output clock pulses generated in the oscilla tion circuit are output as they are.
rs5c372a/b 42 4.1-1 control of the intra , intrb output (flag bit, enable bit, interrupt output select bit) (rs5c372a) of the three output wave forms listed above, interrupt out put conditions may be set by setting the flag bit that monitors output state on the register, the enable bit that enables an output wave form and the output select bit that selects either intra or intrb to be output a wave form to. flag bit enable bit interrupt output select bit (sl 2 , sl 1 ) enable bit (d5, d4 at eh) (0,0) (0,1) (1,0) (1,1) alarm_a aafg (d1 at fh) aale (d7 at eh) intra intra intra intra alarm_b bafg (d0 at fh) bale (d6 at eh) intra intrb intra intrb periodic interrupt ctfg (d2 at fh) disabled at ct 2 ? ? ? ? when power on (xstp ? 1) since aale ? bale ? ct 2 ? ct 1 ? ct 0 ? clen ? sl 2 ? sl 1 ? 0, intra ? off (?h?). 32-khz clock pulses are output from the intrb pin. ? when more than one output wave forms are output from a single output pin, the output will have or wave form of negative logic of both. example: when alarm_a and alarm_b are output from the intra pin. a larm_a a larm_b intra in such a case which output wave form is output from the pin may be confirmed by reading the flag register.
rs5c372a/b 43 4.1-2 alarm interrupt (rs5c372a) for setting an alarm time, designated time such as day-o f-the-week, hour or minute should be set to the alarm registers being aale (bale) bit to 0. after that set th e aale (bale) bit to 1, from this moment onward when such registered alarm time coincide the value of calendar counter the intra or intrb comes down to ?l? (on). the intra or intrb output can be controlled by operating to the aale (bale) and aafg (bafg) bits. alarm-calendar coincidence period (1 min.) day-of- the-week, time matched day-of- the-week, time matched day-of- the-week, time matched day-of- the-week, time matched intr intr aale 1 (bale) aale 1 (bale) aalfg 0 (bafg) aale 0 (bale) aale 0 (bale) aale 1 (bale) a a : max.61.1 s (max. 62.5 s when 32.000khz crystal is used.) ? ) note that aafg (bafg) has an output wave form of reversed logic. 4.2 intr output pin (rs5c372b) the following three output wave forms can be output from the intr pin. 1) alarm interrupt when a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar counter (such as day-of-the-week, hour or minute) interrupt to the cpu are requested wi th the output pin being on (?l?). alarm interrupt consists of alarm_a and alarm_b, both have equivalent functions. 2) periodic interrupt outputs an output wave form selected by setting the per iodic interrupt frequency select bit. wave forms include pulse mode and level mode.
rs5c372a/b 44 4.2-1 control of the intr output (flag bit, enable bit, interrupt output select bit) (rs5c372b) of the two output wave forms listed above, interrupt output conditions may be set by setting the flag bit that monitors output state on the register, the enable bit that enables an output wave form. flag bit enable bit alarm_a aafg (d1 at fh) aale (d7 at eh) alarm_b bafg (d0 at fh) bale (d6 at eh) periodic interrupt ctfg (d2 at fh) disabled at ct 2 ? ct 1 ? ct 0 ? ? when power on (xstp ? 1) since aale ? bale ? ct 2 ? ct 1 ? ct 0 ? 0, intr ? off (?h?). ? when more than one output wave forms are output from a single output pin, the output will have or wave form of negative logic of both. example: when alarm_a and alarm_b are output from the intr pin. a larm_a a larm_b intr in such a case which output wave form is output from the pin may be confirmed by readingthe flag register. 4.2-2 alarm interrupt (rs5c372b) for setting an alarm time, designated time such as day-o f-the-week, hour or minute should be set to the alarm registers being aale (bale) bit to 0. after that set th e aale (bale) bit to 1, fr om this moment onward when such registered alarm time coincide the value of calendar counter the intr comes down to ?l? (on). the intr output can be controlled by operating to the aale (bale) and aafg (bafg) bits. alarm-calendar coincidence period (1 min.) day-of- the-week, time matched day-of- the-week, time matched day-of- the-week, time matched day-of- the-week, time matched intra or intrb intra or intrb aale 1 (bale) aale 1 (bale) aalfg 0 (bafg) aale 0 (bale) aale 0 (bale) aale 1 (bale) a a : max.61.1s (max. 62.5 s when 32.000khz crystal is used.) ? ) note that aafg (bafg) has an output wave form of reversed logic.
rs5c372a/b 45 4.3 periodic (clock) interrupt the intra or intrb pin ( intr for the rs5c372b) output, the periodic interrupt cycle select bits (ct 2 , ct 1 , ct 0 ) and the interrupt output select bits (sl 2 , sl 1 ) can be used to interrupt the cpu in a certain cycle. the periodic interrupt cycle select bits can be used to select either one of two interrupt output modes: the pulse mode and the level mode. interrupt cycle selection ct 2 ct 1 ct 0 description wave from mode cycle and falling timing 0 0 0 ? off (default) 0 0 1 ? fixed at ?l? 0 1 0 pulse mode 2hz (duty50%) 0 1 1 pulse mode 1hz (duty50%) 1 0 0 level mode every second (coincident with second count-up) 1 0 1 level mode every minute (at 00 second) 1 1 0 level mode every hour (at 00:00 on the hour) 1 1 1 level mode every month (1st day, 00:00:00 a.m.) 1) pulse mode : outputs 2hz, 1hz clock pulses. fo r relationships with counting up of seconds see the diagram below. ? ) when 32.000khz crystal is used, in the 2hz clock pulse mode, 0.496s clock pulses and 0.504s clock pulse are output alternately. duty cycle for 1hz clock pulses becomes 50.4% (?l? duration is 0.496s while ?h? duration is 0.504s). 2) level mode: one second, one minute or one month ma y be selected for an interrupt cycle. counting up of seconds is matched with falling edge of interrupt output. 3) when the time trimming circuit is used, per iodic interrupt cycle changes every 20 seconds. pulse mode: ?l? duration of output pulses may change in the maximum range of ? 3.784ms ( ? 3.875ms when 32.000khz crystal is used.) for example, duty will be 50 ? 0.3784% (or 50 ? 0.3875% when 32.000khz crystal is used) at 1hz. level mode: frequency in one second may change in the maximum range of ? 3.784ms ( ? 3.875ms when 32.000khz crystal is used.) relation between mode waveforms and ctfg bit ? pulse mode approx. 92 s (32.768khz crystal is used) approx. 94 s (32.000khz crystal is used) ctfg bit (counting up of seconds) intra or intrb pins (intr pin for the rs5c372b) ? ) since counting up of seconds and the falling edge has a time lag of approx. 92 ? s (at 32.768khz) (approx. 94 ? s when 32.000khz crystal is used), a time may be read with apparently approx. one second delayed from time of the real-time clock when time is read in synchronization with the falling edge of output.
rs5c372a/b 46 ? level mode write 0 to ctfg (second count-up) write 0 to ctfg ctfg bit (second count-up) (second count-up) intra or intrb pins (intr pin for the rs5c372b) 4.4 32-khz clock output ?? rs5c372a the crystal oscillator can generate clock pulses of 32khz from the intrb pin. the pin is changed to ?h? by setting the clen bit to ?1?. ? 1) 32-khz clock output will not be affected from settings in the clock adjustment register. ? 2) when power on (xstp ? 1) 32-khz clock pulses are output from the intrb pin. ?? rs5c372b the crystal oscillator can generate clock pulses of 32kh z from the 32kout pin.the pin is changed to ?off? by setting the clen bit to ?1?. ? 1) 32-khz clock output will not be affected from settings in the clock adjustment register. ? 2) when power on (xstp ? 1) 32-khz clock pulses are output from the 32kout pin. max. 76.3 s max. 76.3 s clen bit setting 32kout pin output (max. 78.1s when 32.000khz crystal is used) (max. 78.1s when 32.000khz crystal is used)
rs5c372a/b 47 5. typical applications 5.1 examples of circuits example 1 rs5c372a/b 32.768khz or 32.000khz a b oscin oscout v dd v ss intra or b (intr) system power suppl * 3 * 2 * 1 *1) mount the high-and low-frequency by-pass capacitors in parallel and very close to the rs5c372a/b. *2) connect the pull-up resistor of the intr a pin or the intrb pin ( intr ) to two different positions depending on whether the resistor is in use during battery back-up: (i) when not in use during battery back-up ??????????? position a in the left figure (ii) when in use during battery back-up ??????????? position b in the left figure *3) intra and intrb for the rs5c372a, intr for the rs5c372b. example 2 rs5c372a/b a b 32.768khz or 32.000khz oscin oscout v dd v ss intra or b (intr) system power suppl * 2 *1) connection in the example shown left may not affect the rs5c372a/b except the 32kout of the rs5c372b since it is designed to be operational even when the pin voltage exceeds v dd . *2) intra and intrb for the rs5c372a, intr for the rs5c372b.
rs5c372a/b 48 5.2 example of interface circuit to the cpu ? rs5c372a v dd microcontrolle r 32.768khz or 32.000khz v dd v ss oscin oscout scl sda intrb rs5c372a intra system power supply backup power supply ? ) the scl and sda pins of the rs5c372a do not contain protective diodes on v dd side. therefore, back up power supply ? system power supply causes no adverse effect. ? rs5c372b v dd microcontrolle r 32.768khz or 32.000khz v dd v ss oscin oscout scl sda intr rs5c372b 32kout system power supply backup power supply ? ) the scl and sda pins of the rs5c372b do not contain protective diodes on v dd side. therefore, back up power supply ? system power supply causes no adverse effect.
rs5c372a/b 49 5.3 example of power supply wake-up circuit (rs5c372a only) the sample circuit below has been designed so that system power supply turns on at a time set in the alarm_b rn5rz a or rn5rt a v dd vout rs5c372a ce v dd microcontrolle r 32.768khz or 32.000khz v dd v ss oscin oscout scl sda intrb system power supply backup power supply * 1 * 2 * 3 * 3 * 4 ? 1) the rn5rz ?? a and the rn5rt ?? a are ricoh regulators with stand-by functions. ? 2) the intrb of the rs5c372a outputs 32-kh z clock pulses on power on. a capacitor is included so that ce will not change to ?h? while 32-khz clock is off (? h?) to allow the regulator to be turned on. ? 3) this resistor is used to prev ent excess current from flowing into the pins of the rs5c372a and the rn5rz ?? a (rn5rt ?? a) on power on. ? 4) pull-up resistors of the scl and sda ar e not shown in the figure for clarity. software setting (1) use periodic interrupt immediately afte r power on to output on (?l?) from the intrb pin. (2) when you want to turn power off use alarm_b or periodic interrupt to set a timing for power on and output it from the intrb .the intrb remains off (?h?) until the timing specified, high voltage is applied to the regulator ce pin thus power for the micro controller is turned off. (3) on reaching the specified timing, the intrb pin switches to on (?l?) and power turns on. hereafter, power is turned off by setting 0 to the bafg or the ctfg and turned on again at a next timing specified.
rs5c372a/b 50 6. typical characteristic measurements ? test circuit 32.768khz oscin oscout v dd v ss intrb (32kout) 8 7 6 4 1 frequency counter * 1 * 1 x'tal : 32.768khz (r 1 ? 30k ? typ.) (c l ? 6pf to 8pf) topt : 25 ? c output pins : open *1) intrb applies to the rs5c372a, and the 32kout applies to the rs5c372b. the rs5c372b does not need pull up resistor. 6.1 standby supply current vs. power supply voltage 6.2 supply current during 32k clock output vs. power spply voltage (rs5c372a) power supply voltage v dd (v) 0 0 1 2 246 standby supply current i dd ( a) (topt=25 , intrb(32kout)=off) power supply voltage v dd (v) 0 0 1 2 246 supply current during 32k clock output i dd ( a) (topt=25 , intrb=open) 6.3 supply current during 32k clock output vs. power spply voltage (rs5c372b) 6.4 supply current during cpu access vs. scl clock frequency 0 0 1 2 3 4 5 6 246 (topt=25 , 32kout=open) power supply voltage v dd (v) supply current during 32k clock output i dd ( a) scl clock frequency(khz) 0 0 10 15 5 20 200 400 600 supply current during access i dd ( a) (topt=25 , sda=open) v dd = 3v v dd = 5v
rs5c372a/b 51 6.5 standby supply current vs. temperature 6.6 oscillation frequency deviation vs. external c g temperature topt( ) ? 60 0 1 2 ? 40 ? 20 80 60 0 20 40 100 standby supply current i dd ( a) (v dd =3.0v, sda=open) external c g (pf) 0 ? 50 ? 10 ? 20 ? 30 ? 40 10 0 515 10 20 oscillation frequency deviation(ppm) (topt=25 , v dd =3v, external c g =0pf standard) 6.7 oscillation frequency deviation vs. power supply volt- 6.8 oscillation frequency deviation vs. temperature power supply voltage v dd (v) 01 ? 5 2 0 1 ? 2 ? 1 ? 4 ? 3 5 3 4 25 34 6 oscillation frequency deviation(ppm) (topt=25 , v dd =3v standard) temperature topt( ) ? 60 ? 40 ? 20 20 0 ? 200 0 ? 40 ? 80 ? 120 ? 160 40 60 80 100 oscillation frequency deviation(ppm) (v dd =3v, topt=25 standard) 6.9 oscillation start time vs. power supply voltage 6.10 vol vs. iol ( intra , intrb or intr pin) *1 power supply voltage v dd (v) 01 34 2 0 500 400 300 200 100 56 oscillation start time(ms) (topt=25 ) v ol (v) 0 0 20 10 30 50 40 0.2 0.8 0.4 0.6 1 i ol (ma) (topt=25 ) * 1 v dd =3v v dd =5v ? 1) avoid continuous flowing of current of 20ma or more to the intra , intrb , or intr pin.
rs5c372a/b 52 7. typical software-based operations 7.1 initialization upon power-on start xstp=1? power-on no yes control register2 (00 ) set clock and calendar counters and interrupt cycles ack not returned or read data is ffh * 3 * 1 * 4 * 5 * 2 ? 1) start access after waiting one to two seconds that ar e required for starting up of oscillation and internal initialization after power on from 0v. ? 2) if access is tried during ic internal initialization period described in ? 1, acknowledge signal may not be output, it is output only at first, or values read may ffh . if any of these occurs, repeat accessing. this will be required also for ordinary routines when accessing may require 0.5 seconds or more. ? 3) when xstp ? 0 in oscillation halt sensing, it indicates pow er has not been booted from 0v but from back up supply. ? 4) the xstp shall be set to 0 by setting any data to the control register 2. ? 5) perform ordinary initial setting including clock calendar or interrupt cycle. 7.2 write operation to clock and calendar counters stop condition start condition write to clock and calendar counters * 1 * 2 ? 1) when writing to clock and calendar counters, do not insert stop condition until all times from second to year have been written to prevent error in writing time. ? 2) take care so that process from start condition to stop condition will be completed within 0.5 seconds. (the rs5c372a/b force access to the cpu to terminate within 0.5 to 1.0 seconds after start condition has occurred in case the cpu is failed during access.)
rs5c372a/b 53 7.3 read operation from clock and calendar counters stop condition start condition read from clock and calendar counters * 1 * 2 ? 1) when reading from clock and calendar counters, do not insert stop condition until all times from second to year have been read to prevent error in reading time. ? 2) take care so that process from start condition to stop condition will be completed within 0.5 seconds. (the rs5c372a/b force access to the cpu to terminate within 0.5 to 1.0 seconds after start condition has occurred in case the cpu is failed during access.) 7.4 second digit adjustment by ? 30 seconds control register 2 (00 1 111) * 1 ? 1) write 1 to the adj bit. (the ? 30 seconds of adjustment is made within 122.1 ? s (125 ? s when 32.000khz crystal is used) after the adj bit is set to 1.) 7.5 interrupt operation 7.5-1 periodic interrupt operation ctfg=1? periodic interrupt operation other interrupt operation interrupt to cpu control register 2 (00 011) set periodic interrupt cycle select bit and interrupt output select bit yes no * 1 * 2 *1) the level mode is used for the periodic interrupt cycle select bit. *2) interrupt to the cpu is cancelled by setting the ctfg bit to 0.
rs5c372a/b 54 7.5-2 alarm interrupt operation aafg(bafg)=1? interrupt to cpu aale or bale=1 aale or bale=0 set alarm (hour or minute, day-of-the-week) interrupt output select set bits no yes * 1 * 2 * 3 alarm interrupt operation other interrupt operation control register 2 (00 101) *1) before setting alarm time, disable alarm function tentatively by setting aale or bale to 0 in case the set time agrees with the current time. *2) after all alarm settings have been completed, enable alarm function. *3) tentatively unlock alarm. write (00 ??? 101) when alarm_a is used. write (00 ??? 110) when alarm_b is used.
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